The present invention relates to semiconductor integrated circuit devices.
Cells in a semiconductor integrated circuit device include general logic cells and large scale cells. General logic cells are disposed in separate regions of a macro cell region and a wiring region. In the macro cell region, logic elements constructed of a plurality of transistors or the like are formed. Large scale cells, typically memory cells, are disposed on the basis of optimized design for the purpose of improving the operation speed, integration, and the like, so that there is no separation between the macro cell region and the wiring region.
FIG. 3 is a schematic diagram briefly showing the structure of a conventional semiconductor integrated circuit device. In this example, a large scale cell array 22 and general logic cell arrays 23a and 23b are disposed as shown, the large scale cell array 22 and the general logic cell arrays 23a and 23b being interconnected by signal lines 31 and 32. The general logic cell arrays 23a and 23b are interconnected by wiring 35. The large scale cell array 22 has macro cells and wirings contributing only to the operation function of the array 22, and there is no through wiring 34 not directly contributing to the operation function.
The reason for this is as follows. The large scale cell array, for example, a memory cell array, includes cells of small size and capacity. The amplitude between logical signal levels "0" and "1" is set small at sense amplifiers, word lines and bit lines in order to realize high speed operation. Therefore, if a through wiring 34 not directly contributing to the operation function of the large scale cell array 22 passes through this array, there is ample possibility of a malfunction caused by crosstalk noises from a large amplitude signals on the through wiring 34. For this reason, the through wiring 34 is disposed so as not to pass through this array 22.
However, since the through wiring 34 is not allowed to pass through the large scale cell array 22, the general logic cell arrays 23a and 23b are required to be interconnected by a wiring 33 which by-passes the large scale cell array 22, hindering high integration. Such poor integration poses a serious problem under the present technical progress of wiring techniques for three-layers or more, and even four-layers.